Hongduo Liu
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Hongduo Liu, Ph.D. Student |
Biography
I am currently a researcher at Noah’s Ark Lab, Huawei Hong Kong Research Center. I got my Ph.D. in Computer Science from The Chinese University of Hong Kong (CUHK) in July 2025, where I was advised by Prof. Bei Yu and Prof. Tsung-Yi Ho (starting Fall 2021). Earlier, I received my Bachelor's Degree in IoT Engineering and Applied Mathematics from University of Electronic Science and Technology of China (UESTC) in 2020.
Research Interest
Hardware/Software Co-Design
Verification
Electronic Design Automation
Publication
[C9] Mengjia Dai, Hongduo Liu, Yuhao Ji, Xiaojing Su, Yibo Lin, Bei Yu, “Soft-Constrained Triple Patterning Layout Decomposition”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Verona, Italy, Apr. 20–22, 2026.
[C8] Hongduo Liu, Yuntao Lu, Mingjun Wang, Xufeng Yao, Bei Yu, “LLM-Assisted Circuit Verification: A Comprehensive Survey”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Hong Kong, Jan. 19–22, 2026. (Invited Paper)
[C7] Hongduo Liu, Chen BAI, Peng Xu, Lihao Yin, Xianzhi Yu, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu, “LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.
[C6] Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu, “NeuroSelect: Learning to Select Clauses in SAT Solvers”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.
[C5] Hongduo Liu, Peiyu Liao, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu, “Parallel Grobner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25–27, 2024.
[C4] Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin Wong, “On a Moreau Envelope Wirelength Model for Analytical Global Placement”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 09–13, 2023.
[C3] Hongduo Liu, Peiyu Liao, Mengchuan Zou, Bowen Pang, Xijun Li, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu, “Layout Decomposition via Boolean Satisfiability”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 09–13, 2023.
[C2] Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu, “DevelSet: Deep Neural Level Set for Instant Mask optimization”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 1–4, 2021.
[C1] Jiahao Liu, Zhen Zhu, Yong Zhou, Ning Wang, Guanghai Dai, Qingsong Liu, Jianbiao Xiao, Yuxiang Xie, Zirui Zhong, Hongduo Liu, Liang Chang, Jun Zhou, “BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 13–22, 2021.
[J5] Hongduo Liu, Siting Liu, Zhongdong Qi, Tsung-Yi Ho, Bei Yu, “Selecting Nets to Rip Up and Reroute via SAT”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[J4] Hongduo Liu, Peiyu Liao, Mengchuan Zou, Bowen Pang, Xijun Li, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu, “Layout Decomposition via Boolean Satisfiability”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 44, no. 03, pp. 1112–1125, 2025.
[J3] Hongduo Liu, Yijian Qian, Youqiang Liang, Bin Zhang, Zhaohan Liu, Tao He, Wenqian Zhao, Jiangbo Lu, Bei Yu, “A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 29, no. 3, pp. 1–25, 2024.
[J2] Jiahao Liu, Jiajing Fan, Zirui Zhong, Hui Qiu, Jianbiao Xiao, Yong Zhou, Zhen Zhu, Guanghai Dai, Ning Wang, Qingsong Liu, Yuxiang Xie, Hongduo Liu, Liang Chang, Jun Zhou, “An Ultra-low Power Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Wearable Intelligent Health Monitoring”, IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), vol. 17, no. 5, pp. 952-967, 2023.
[J1] Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu, “DevelSet: Deep Neural Level Set for Instant Mask Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 12, pp. 5020–5033, 2023.
Experience
SmartMore
C++ Engineer
Shenzhen, P.R.China, Aug.2020 - Jun.2021
Huawei Noah's Ark Lab
Intern
Hong Kong SAR, China, Aug.2024 - April.2025
Awards
Full Postgraduate Studentship, CUHK, 2021-2025
Outstanding Graduate, UESTC, 2020
First Class Outstanding Academic Scholarship, UESTC, 2017, 2018, 2019